diff options
| author | Samuel Pitoiset <[email protected]> | 2018-01-25 15:46:51 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-01-26 12:14:27 +0100 |
| commit | 6d07e443bac8c894e760a9ca00b4472dd9795ac0 (patch) | |
| tree | 6d2eb4bf1c6d1a21380a0c863ec60f17dc9a533c /src/amd/vulkan | |
| parent | 5391de126294a107ef0db36ae92d9383ece045d3 (diff) | |
radv: fix RADV_DEBUG=syncshaders on GFX9
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index ba5fd92f2a1..b694174de68 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -433,13 +433,22 @@ radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flush_bits flags) { if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) { + uint32_t *ptr = NULL; + uint64_t va = 0; + assert(flags & (RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_CS_PARTIAL_FLUSH)); + if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { + va = radv_buffer_get_va(cmd_buffer->gfx9_fence_bo) + + cmd_buffer->gfx9_fence_offset; + ptr = &cmd_buffer->gfx9_fence_idx; + } + /* Force wait for graphics or compute engines to be idle. */ si_cs_emit_cache_flush(cmd_buffer->cs, false, cmd_buffer->device->physical_device->rad_info.chip_class, - NULL, 0, + ptr, va, radv_cmd_buffer_uses_mec(cmd_buffer), flags); } |