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authorDave Airlie <[email protected]>2016-11-02 00:33:33 +0000
committerDave Airlie <[email protected]>2016-11-03 08:26:51 +1000
commit73592b92844af3c1298ef5e66e3055793443546d (patch)
tree1f52ffd648d54650aea9343d5824cb8e9db7a66e /src/amd/vulkan
parent1d75d681d37a47cf2b3d03b3c32bd9be9751e034 (diff)
radv: fix dual source blending
Dolphin tried to use this, but we hadn't had any tests for it properly. All that is required is the shader output format needs to be set for 0 and 1 exports. Cc: "13.0" <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
-rw-r--r--src/amd/vulkan/radv_pipeline.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d92fbf81d93..fe1eac8743d 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -642,7 +642,8 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
const VkGraphicsPipelineCreateInfo *pCreateInfo,
uint32_t blend_enable,
uint32_t blend_need_alpha,
- bool single_cb_enable)
+ bool single_cb_enable,
+ bool blend_mrt0_is_dual_src)
{
RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
@@ -664,6 +665,8 @@ radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
blend->cb_shader_mask = si_get_cb_shader_mask(col_format);
+ if (blend_mrt0_is_dual_src)
+ col_format |= (col_format & 0xf) << 4;
if (!col_format)
col_format |= V_028714_SPI_SHADER_32_R;
blend->spi_shader_col_format = col_format;
@@ -715,6 +718,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
struct radv_blend_state *blend = &pipeline->graphics.blend;
unsigned mode = V_028808_CB_NORMAL;
uint32_t blend_enable = 0, blend_need_alpha = 0;
+ bool blend_mrt0_is_dual_src = false;
int i;
bool single_cb_enable = false;
if (extra && extra->custom_blend_mode) {
@@ -755,7 +759,9 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
}
if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
- radv_finishme("dual source blending");
+ if (i == 0)
+ blend_mrt0_is_dual_src = true;
+
if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
srcRGB = VK_BLEND_FACTOR_ONE;
dstRGB = VK_BLEND_FACTOR_ONE;
@@ -797,7 +803,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
blend->cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo,
- blend_enable, blend_need_alpha, single_cb_enable);
+ blend_enable, blend_need_alpha, single_cb_enable, blend_mrt0_is_dual_src);
}
static uint32_t si_translate_stencil_op(enum VkStencilOp op)