diff options
| author | Samuel Pitoiset <[email protected]> | 2019-12-06 12:12:38 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-12-10 11:04:40 +0100 |
| commit | 4f659224c850706db37e01235af96122b7cd1407 (patch) | |
| tree | 5065a67cad8109056b88b0999034ca9db403408e /src/amd/vulkan | |
| parent | 87f7ec8a2ca393100bddb37f0b83488d7c158d4d (diff) | |
radv: move emission of two PA_SC_* registers to the pipeline CS
They don't have to be updated dynamically.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 5 | ||||
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 2 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d655f6e2313..5850172d127 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -874,12 +874,9 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples) return; - radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2); - radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl); + radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config); - radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); - radv_emit_default_sample_locations(cmd_buffer->cs, num_samples); /* GFX9: Flush DFSM when the AA mode changes. */ diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 95b1684fdf8..aa97137c7fd 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -3648,7 +3648,9 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]); radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); + radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); + radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl); /* The exclusion bits can be set to improve rasterization efficiency * if no sample lies on the pixel boundary (-8 sample offset). It's |