diff options
| author | Nicolai Hähnle <[email protected]> | 2017-05-10 22:25:15 +0200 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-06-05 10:43:59 +1000 |
| commit | e156eaedb4a9c018c6381c1d59743ec2659aff37 (patch) | |
| tree | f5217419113eb8b06bfac9ee24901e60df5136b7 /src/amd/vulkan/winsys | |
| parent | 34b7fb47b603638480183d095303cfd66b824d0b (diff) | |
radv: remove radeon_surf_level::nblk_z
We're not using thick tiling modes, so we can just derive the value
ourselves.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/winsys')
| -rw-r--r-- | src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c index ab1f9520b44..44b1c8f6190 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c @@ -205,10 +205,6 @@ static int radv_compute_level(ADDR_HANDLE addrlib, surf_level->slice_size = AddrSurfInfoOut->sliceSize; surf_level->nblk_x = AddrSurfInfoOut->pitch; surf_level->nblk_y = AddrSurfInfoOut->height; - if (type == RADEON_SURF_TYPE_3D) - surf_level->nblk_z = AddrSurfInfoOut->depth; - else - surf_level->nblk_z = 1; switch (AddrSurfInfoOut->tileMode) { case ADDR_TM_LINEAR_ALIGNED: |