diff options
| author | Nicolai Hähnle <[email protected]> | 2017-05-10 22:20:37 +0200 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-06-05 10:43:56 +1000 |
| commit | 34b7fb47b603638480183d095303cfd66b824d0b (patch) | |
| tree | d72b1500d8ddc90f2b4b2ef03f1052524ed4f3da /src/amd/vulkan/winsys | |
| parent | 59f72e158aa0349085ef25900eb1651aa67ec67f (diff) | |
radv: remove radeon_surf_level::dcc_enabled
Like radeonsi; replace with radeon_surf::num_dcc_levels.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/winsys')
| -rw-r--r-- | src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c index f8e22da16b6..ab1f9520b44 100644 --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_surface.c @@ -233,7 +233,6 @@ static int radv_compute_level(ADDR_HANDLE addrlib, /* Clear DCC fields at the beginning. */ surf_level->dcc_offset = 0; - surf_level->dcc_enabled = false; /* The previous level's flag tells us if we can use DCC for this level. */ if (AddrSurfInfoIn->flags.dccCompatible && @@ -251,7 +250,7 @@ static int radv_compute_level(ADDR_HANDLE addrlib, if (ret == ADDR_OK) { surf_level->dcc_offset = surf->dcc_size; surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize; - surf_level->dcc_enabled = true; + surf->num_dcc_levels = level + 1; surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize; surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign); } @@ -476,6 +475,7 @@ static int radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, } surf->bo_size = 0; + surf->num_dcc_levels = 0; surf->dcc_size = 0; surf->dcc_alignment = 1; surf->htile_size = surf->htile_slice_size = 0; |