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authorBas Nieuwenhuizen <[email protected]>2017-04-26 00:04:46 +0200
committerBas Nieuwenhuizen <[email protected]>2017-04-26 01:32:41 +0200
commit7b9963a28f432920428f7fac5f6dba7b2996cd16 (patch)
treeba9c3240da7641b89e2cf77e225de8dc16527779 /src/amd/vulkan/winsys/amdgpu
parentee5f96581ad694cc61cf83bc7022bd71c36bfe08 (diff)
radv: Enable userspace fence checking.
v2: - Added some error handling. - memset the buffer to 0. v3: Added assert for buffer size. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/winsys/amdgpu')
-rw-r--r--src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c27
-rw-r--r--src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c9
-rw-r--r--src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h3
3 files changed, 36 insertions, 3 deletions
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 8430df4d0fe..7e464308564 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -117,16 +117,24 @@ static bool radv_amdgpu_fence_wait(struct radeon_winsys *_ws,
bool absolute,
uint64_t timeout)
{
+ struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)_ws;
struct amdgpu_cs_fence *fence = (struct amdgpu_cs_fence *)_fence;
unsigned flags = absolute ? AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE : 0;
int r;
uint32_t expired = 0;
+ if (ws->fence_map) {
+ if (ws->fence_map[fence->ip_type * MAX_RINGS_PER_TYPE + fence->ring] >= fence->fence)
+ return true;
+ if (!absolute && !timeout)
+ return false;
+ }
+
/* Now use the libdrm query. */
r = amdgpu_cs_query_fence_status(fence,
- timeout,
- flags,
- &expired);
+ timeout,
+ flags,
+ &expired);
if (r) {
fprintf(stderr, "amdgpu: radv_amdgpu_cs_query_fence_status failed.\n");
@@ -619,6 +627,16 @@ static int radv_amdgpu_create_bo_list(struct radv_amdgpu_winsys *ws,
return r;
}
+static struct amdgpu_cs_fence_info radv_set_cs_fence(struct radv_amdgpu_winsys *ws, int ip_type, int ring)
+{
+ struct amdgpu_cs_fence_info ret = {0};
+ if (ws->fence_map) {
+ ret.handle = radv_amdgpu_winsys_bo(ws->fence_bo)->bo;
+ ret.offset = (ip_type * MAX_RINGS_PER_TYPE + ring) * sizeof(uint64_t);
+ }
+ return ret;
+}
+
static void radv_assign_last_submit(struct radv_amdgpu_ctx *ctx,
struct amdgpu_cs_request *request)
{
@@ -676,6 +694,7 @@ static int radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx,
request.number_of_ibs = 1;
request.ibs = &cs0->ib;
request.resources = bo_list;
+ request.fence_info = radv_set_cs_fence(cs0->ws, cs0->hw_ip, queue_idx);
if (initial_preamble_cs) {
request.ibs = ibs;
@@ -740,6 +759,7 @@ static int radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx,
request.resources = bo_list;
request.number_of_ibs = cnt + !!preamble_cs;
request.ibs = ibs;
+ request.fence_info = radv_set_cs_fence(cs0->ws, cs0->hw_ip, queue_idx);
if (preamble_cs) {
ibs[0] = radv_amdgpu_cs(preamble_cs)->ib;
@@ -858,6 +878,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx,
request.resources = bo_list;
request.number_of_ibs = 1;
request.ibs = &ib;
+ request.fence_info = radv_set_cs_fence(cs0->ws, cs0->hw_ip, queue_idx);
r = amdgpu_cs_submit(ctx->ctx, 0, &request, 1);
if (r) {
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
index 783567fa5b4..837493c0672 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c
@@ -342,6 +342,7 @@ static void radv_amdgpu_winsys_destroy(struct radeon_winsys *rws)
{
struct radv_amdgpu_winsys *ws = (struct radv_amdgpu_winsys*)rws;
+ ws->base.buffer_destroy(ws->fence_bo);
AddrDestroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
FREE(rws);
@@ -380,6 +381,14 @@ radv_amdgpu_winsys_create(int fd, uint32_t debug_flags)
radv_amdgpu_cs_init_functions(ws);
radv_amdgpu_surface_init_functions(ws);
+ assert(AMDGPU_HW_IP_NUM * MAX_RINGS_PER_TYPE * sizeof(uint64_t) <= 4096);
+ ws->fence_bo = ws->base.buffer_create(&ws->base, 4096, 8,
+ RADEON_DOMAIN_GTT,
+ RADEON_FLAG_CPU_ACCESS);
+ if (ws->fence_bo)
+ ws->fence_map = (uint64_t*)ws->base.buffer_map(ws->fence_bo);
+ if (ws->fence_map)
+ memset(ws->fence_map, 0, 4096);
return &ws->base;
winsys_fail:
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
index abb238b358d..c136da0c1ec 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.h
@@ -50,6 +50,9 @@ struct radv_amdgpu_winsys {
unsigned num_buffers;
bool use_ib_bos;
+
+ struct radeon_winsys_bo *fence_bo;
+ uint64_t *fence_map;
};
static inline struct radv_amdgpu_winsys *