diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-12-30 17:31:44 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-12-31 15:07:07 +0100 |
| commit | 6a36bfc64d2096aa338958c4605f5fc6372c07b8 (patch) | |
| tree | 3a59c9fd9a30dcf09cb004511979d2010aa0829d /src/amd/vulkan/si_cmd_buffer.c | |
| parent | b0d17270ada1b7292f09b5d4ab2c77880ee64c35 (diff) | |
radv: Implement binning on GFX9.
Overall it does not really help or hurt. The deferred demo gets 1%
improvement and some games a 3% decrease, so I don't think this
should be enabled by default.
But with the code upstream it is easier to experiment with it.
v2: Remove initializing the registers from si_emit_config.
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/si_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index a6981c136e7..68913ec2ad3 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -518,12 +518,6 @@ si_emit_config(struct radv_physical_device *physical_device, assert(0); } - radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, - S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF)); - /* TODO: Enable the binner: */ - radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0, - S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) | - S_028C44_DISABLE_START_OF_PRIM(1)); radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1, S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) | S_028C48_MAX_PRIM_PER_BATCH(1023)); |