diff options
| author | Samuel Pitoiset <[email protected]> | 2018-06-20 16:10:55 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-06-21 10:31:02 +0200 |
| commit | 41f6096c26860e02d4377e58d93454965531ece8 (patch) | |
| tree | 44de6f037b93d198868c8e51e61925c921aac76e /src/amd/vulkan/si_cmd_buffer.c | |
| parent | 53959fcbd88f38316359aa7b48cb9464c23eb870 (diff) | |
radv: use EOP_DATA_SEL_* instead of magic numbers
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/si_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/si_cmd_buffer.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index a663d2add6d..d6b073c7838 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -799,7 +799,9 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, chip_class, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, - 0, 0, 0, 0, 0); + 0, + EOP_DATA_SEL_DISCARD, + 0, 0, 0); } } if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) { @@ -867,7 +869,8 @@ si_cs_emit_cache_flush(struct radeon_cmdbuf *cs, assert(flush_cnt); uint32_t old_fence = (*flush_cnt)++; - si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, 1, + si_cs_emit_write_event_eop(cs, false, chip_class, false, cb_db_event, tc_flags, + EOP_DATA_SEL_VALUE_32BIT, flush_va, old_fence, *flush_cnt); si_emit_wait_fence(cs, false, flush_va, *flush_cnt, 0xffffffff); } |