diff options
| author | Samuel Pitoiset <[email protected]> | 2019-07-05 08:33:06 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-07-07 17:51:32 +0200 |
| commit | ee21bd7440c3222cc01a630c4ef49d33bf431807 (patch) | |
| tree | 295fbba66f84642e9c82506bb78b2f0b605347a3 /src/amd/vulkan/radv_shader.c | |
| parent | 9e37609d0bc1246a880571e78a169678bc9acf48 (diff) | |
radv/gfx10: implement NGG support (VS only)
This needs to be cleaned up a bit, and it probably contains
missing stuff and/or bugs.
This doesn't fix the "half of the triangles" issue.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_shader.c')
| -rw-r--r-- | src/amd/vulkan/radv_shader.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 315d522b63e..d36dfbdf332 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -583,7 +583,9 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); break; case MESA_SHADER_VERTEX: - if (info->vs.as_ls) { + if (info->is_ngg) { + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + } else if (info->vs.as_ls) { assert(pdevice->rad_info.chip_class <= GFX8); /* We need at least 2 components for LS. * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID). @@ -632,8 +634,19 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, break; } - if (pdevice->rad_info.chip_class >= GFX9 && - stage == MESA_SHADER_GEOMETRY) { + if (pdevice->rad_info.chip_class >= GFX10 && + stage == MESA_SHADER_VERTEX) { + unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; + + /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */ + es_vgpr_comp_cnt = info->info.vs.needs_instance_id ? 3 : 0; + gs_vgpr_comp_cnt = 3; + + config_out->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt); + config_out->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) | + S_00B22C_LDS_SIZE(config_in->lds_size); + } else if (pdevice->rad_info.chip_class >= GFX9 && + stage == MESA_SHADER_GEOMETRY) { unsigned es_type = info->gs.es_type; unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt; |