diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2019-07-06 12:31:25 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-07-07 17:51:32 +0200 |
| commit | aeb5b1a998552a815d3dda296e0155a33900f653 (patch) | |
| tree | 2f27aa2c24510e6bc4f4ab6de88ca0e32a76c4f3 /src/amd/vulkan/radv_shader.c | |
| parent | 67b6888d8b69db5d5f1fb9354defe4cc0f519275 (diff) | |
radv/gfx10: Set MEM_ORDERED flags on shaders.
Scattered because depending on stage they are at offset 24/25/27/30.
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_shader.c')
| -rw-r--r-- | src/amd/vulkan/radv_shader.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c index 2f7c2f15b06..315d522b63e 100644 --- a/src/amd/vulkan/radv_shader.c +++ b/src/amd/vulkan/radv_shader.c @@ -565,6 +565,8 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, } else { bool enable_prim_id = info->tes.export_prim_id || info->info.uses_prim_id; vgpr_comp_cnt = enable_prim_id ? 3 : 2; + + config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); } config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); break; @@ -578,6 +580,7 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, } else { config_out->rsrc2 |= S_00B12C_OC_LDS_EN(1); } + config_out->rsrc1 |= S_00B428_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); break; case MESA_SHADER_VERTEX: if (info->vs.as_ls) { @@ -603,12 +606,18 @@ static void radv_postprocess_config(const struct radv_physical_device *pdevice, } else { vgpr_comp_cnt = 0; } + + config_out->rsrc1 |= S_00B128_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); } break; case MESA_SHADER_FRAGMENT: + config_out->rsrc1 |= S_00B028_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); + break; case MESA_SHADER_GEOMETRY: + config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); break; case MESA_SHADER_COMPUTE: + config_out->rsrc1 |= S_00B848_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); config_out->rsrc2 |= S_00B84C_TGID_X_EN(info->info.cs.uses_block_id[0]) | S_00B84C_TGID_Y_EN(info->info.cs.uses_block_id[1]) | |