diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-03-07 00:37:46 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-03-07 09:58:21 +0100 |
| commit | dbecbab5aa6fec9d90089ff5e16bc74339edb955 (patch) | |
| tree | 4bdd9e51136561248bbc47fba3882cb6f8fa4ecf /src/amd/vulkan/radv_radeon_winsys.h | |
| parent | 03f5405fc2fa718ddab36e244f1abd2f038df777 (diff) | |
radv/amdgpu: Let addrlib calculate the HTILE parameters.
Still not sure we can support miptrees when sampling from
HTILE enabled textures.
Added the tcCompatible winsys stuff while I'm at it.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_radeon_winsys.h')
| -rw-r--r-- | src/amd/vulkan/radv_radeon_winsys.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 8cf29a38d94..a8a1d2e369f 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -148,6 +148,7 @@ struct radeon_info { #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) #define RADEON_SURF_FMASK (1 << 21) #define RADEON_SURF_DISABLE_DCC (1 << 22) +#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) @@ -217,6 +218,10 @@ struct radeon_surf { uint64_t dcc_size; uint64_t dcc_alignment; + + uint64_t htile_size; + uint64_t htile_slice_size; + uint64_t htile_alignment; }; enum radeon_bo_layout { |