diff options
| author | Samuel Pitoiset <[email protected]> | 2020-03-03 14:24:55 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2020-03-10 10:05:40 +0100 |
| commit | 24db276d11976905b2e8a44965c684bb48c3d49f (patch) | |
| tree | e9153aaa949fb8e9913abea7e7d9e75e9e3c005c /src/amd/vulkan/radv_private.h | |
| parent | c04e9befc0d3eaa4ec8e04af39a11f98c4a659ba (diff) | |
radv/sqtt: describe pipeline and wait events barriers
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4031>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e4c6a67032c..83a41a607a3 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -2424,6 +2424,30 @@ int radv_dump_thread_trace(struct radv_device *device, const struct radv_thread_trace *trace); /* radv_sqtt_layer_.c */ +/** + * Value for the reason field of an RGP barrier start marker originating from + * the Vulkan client (does not include PAL-defined values). (Table 15) + */ +enum rgp_barrier_reason { + RGP_BARRIER_UNKNOWN_REASON = 0xFFFFFFFF, + + /* External app-generated barrier reasons, i.e. API synchronization + * commands Range of valid values: [0x00000001 ... 0x7FFFFFFF]. + */ + RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER = 0x00000001, + RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC = 0x00000002, + RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS = 0x00000003, + + /* Internal barrier reasons, i.e. implicit synchronization inserted by + * the Vulkan driver Range of valid values: [0xC0000000 ... 0xFFFFFFFE]. + */ + RGP_BARRIER_INTERNAL_BASE = 0xC0000000, + RGP_BARRIER_INTERNAL_PRE_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 0, + RGP_BARRIER_INTERNAL_POST_RESET_QUERY_POOL_SYNC = RGP_BARRIER_INTERNAL_BASE + 1, + RGP_BARRIER_INTERNAL_GPU_EVENT_RECYCLE_STALL = RGP_BARRIER_INTERNAL_BASE + 2, + RGP_BARRIER_INTERNAL_PRE_COPY_QUERY_POOL_RESULTS_SYNC = RGP_BARRIER_INTERNAL_BASE + 3 +}; + void radv_describe_begin_cmd_buffer(struct radv_cmd_buffer *cmd_buffer); void radv_describe_end_cmd_buffer(struct radv_cmd_buffer *cmd_buffer); void radv_describe_draw(struct radv_cmd_buffer *cmd_buffer); @@ -2431,6 +2455,9 @@ void radv_describe_dispatch(struct radv_cmd_buffer *cmd_buffer, int x, int y, in void radv_describe_begin_render_pass_clear(struct radv_cmd_buffer *cmd_buffer, VkImageAspectFlagBits aspects); void radv_describe_end_render_pass_clear(struct radv_cmd_buffer *cmd_buffer); +void radv_describe_barrier_start(struct radv_cmd_buffer *cmd_buffer, + enum rgp_barrier_reason reason); +void radv_describe_barrier_end(struct radv_cmd_buffer *cmd_buffer); struct radeon_winsys_sem; |