diff options
| author | Matthew Nicholls <[email protected]> | 2018-01-29 16:26:18 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-01-31 13:37:18 +1000 |
| commit | ef272b161e05e8216f2d1f4df5023f3aed0ae4fa (patch) | |
| tree | 7e4267a88bc19c40e8d5e0d1e7bc126ec7d99c11 /src/amd/vulkan/radv_private.h | |
| parent | 1ea9efd2f8892cc238b12ec3f329e8322a9e5d2f (diff) | |
radv: remove predication on cache flushes
This can lead to a situation where cache flushes could get conditionally
disabled while still clearing the flush_bits, and thus flushes due to
application pipeline barriers may never get executed.
Fixes: a6c2001ace (radv: add support for cmd predication.)
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 503881fc83b..6239e331839 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1021,7 +1021,6 @@ void si_emit_wait_fence(struct radeon_winsys_cs *cs, uint64_t va, uint32_t ref, uint32_t mask); void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, - bool predicated, enum chip_class chip_class, uint32_t *fence_ptr, uint64_t va, bool is_mec, |