diff options
| author | Dave Airlie <[email protected]> | 2017-06-06 09:01:48 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-06-06 09:43:40 +1000 |
| commit | c2fbeb7ca057b3bee8c8cd0f7076af2b90d28111 (patch) | |
| tree | 4e8263e1a9be4ba109e76008bdafe642778db081 /src/amd/vulkan/radv_private.h | |
| parent | b11c4a554681607bbec67f45442b815b51573236 (diff) | |
radv: add GFX9 cache flushing support.
GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index e1b9a29cee1..6a6c1e2351a 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -822,6 +822,9 @@ struct radv_cmd_buffer { bool record_fail; int ring_offsets_idx; /* just used for verification */ + uint32_t gfx9_fence_offset; + struct radeon_winsys_bo *gfx9_fence_bo; + uint32_t gfx9_fence_idx; }; struct radv_image; @@ -854,9 +857,10 @@ void si_emit_wait_fence(struct radeon_winsys_cs *cs, uint64_t va, uint32_t ref, uint32_t mask); void si_cs_emit_cache_flush(struct radeon_winsys_cs *cs, - enum chip_class chip_class, - bool is_mec, - enum radv_cmd_flush_bits flush_bits); + enum chip_class chip_class, + uint32_t *fence_ptr, uint64_t va, + bool is_mec, + enum radv_cmd_flush_bits flush_bits); void si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer); void si_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, |