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authorDave Airlie <[email protected]>2017-03-30 08:18:13 +0100
committerDave Airlie <[email protected]>2017-04-01 07:16:19 +1000
commit4c60c68bd16486dfb57ba177487bc599ad3ef9f5 (patch)
treeb5f49b6b6d233ce127b5d27836b7cd8912f587b5 /src/amd/vulkan/radv_private.h
parent823b55a8a90ad1cb9a3f9652cf46789f5e0b79f5 (diff)
radv/pipeline: start calculating tess stage.
This calculates the pipeline state for tessellation. It moves the gs ring calculation down to below where the tessellation shaders will be compiled, as it needs the info from those shaders. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
-rw-r--r--src/amd/vulkan/radv_private.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d6982d826aa..3f92d59ac97 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -936,6 +936,18 @@ struct radv_prim_vertex_count {
uint8_t incr;
};
+struct radv_tessellation_state {
+ uint32_t ls_hs_config;
+ uint32_t tcs_in_layout;
+ uint32_t tcs_out_layout;
+ uint32_t tcs_out_offsets;
+ uint32_t offchip_layout;
+ unsigned num_patches;
+ unsigned lds_size;
+ unsigned num_tcs_input_cp;
+ uint32_t tf_param;
+};
+
struct radv_pipeline {
struct radv_device * device;
uint32_t dynamic_state_mask;
@@ -962,6 +974,7 @@ struct radv_pipeline {
struct radv_depth_stencil_state ds;
struct radv_raster_state raster;
struct radv_multisample_state ms;
+ struct radv_tessellation_state tess;
uint32_t db_shader_control;
uint32_t shader_z_format;
unsigned prim;