diff options
| author | Samuel Pitoiset <[email protected]> | 2018-06-22 19:16:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-06-26 18:23:16 +0200 |
| commit | fa42fa1a60debf26cdf86f40c0c805b0fc3b444f (patch) | |
| tree | 85282c42ab1e02cb43f2b6459bdb6ada50d7183a /src/amd/vulkan/radv_private.h | |
| parent | ab2643e4b06f63c93a57624003679903442634a8 (diff) | |
radv: emit PIPELINESTAT_{START,STOP} events for pipeline stats queries
Ported from RadeonSI.
This appears to fix some random fails with:
dEQP-VK.query_pool.statistics_query.*
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index f001b836c8f..a202697e935 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -833,6 +833,9 @@ enum radv_cmd_flush_bits { RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10, RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11, RADV_CMD_FLAG_VGT_FLUSH = 1 << 12, + /* Pipeline query controls. */ + RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13, + RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14, RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META | @@ -966,6 +969,7 @@ struct radv_cmd_state { enum radv_cmd_flush_bits flush_bits; unsigned active_occlusion_queries; bool perfect_occlusion_queries_enabled; + unsigned active_pipeline_queries; float offset_scale; uint32_t trace_id; uint32_t last_ia_multi_vgt_param; |