diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-25 17:57:45 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-06-25 18:38:37 +0200 |
| commit | 8ea7ee153649ac07c8418cc0d4aa5a4e123d19d1 (patch) | |
| tree | 05b4740f8d00e8de9c3d9b0ff0c896dab358b6dd /src/amd/vulkan/radv_private.h | |
| parent | 5411f470564f6f1c2a55d037103f051cbddd5623 (diff) | |
radv: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 44 |
1 files changed, 24 insertions, 20 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index b537778001c..0c842a4d1b7 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -914,29 +914,33 @@ enum radv_cmd_dirty_bits { }; enum radv_cmd_flush_bits { - RADV_CMD_FLAG_INV_ICACHE = 1 << 0, - /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */ - RADV_CMD_FLAG_INV_SMEM_L1 = 1 << 1, - /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */ - RADV_CMD_FLAG_INV_VMEM_L1 = 1 << 2, - /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */ - RADV_CMD_FLAG_INV_GLOBAL_L2 = 1 << 3, - /* Same as above, but only writes back and doesn't invalidate */ - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 = 1 << 4, + /* Instruction cache. */ + RADV_CMD_FLAG_INV_ICACHE = 1 << 0, + /* Scalar L1 cache. */ + RADV_CMD_FLAG_INV_SCACHE = 1 << 1, + /* Vector L1 cache. */ + RADV_CMD_FLAG_INV_VCACHE = 1 << 2, + /* L2 cache + L2 metadata cache writeback & invalidate. + * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */ + RADV_CMD_FLAG_INV_L2 = 1 << 3, + /* L2 writeback (write dirty L2 lines to memory for non-L2 clients). + * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8. + * GFX6-7 will do complete invalidation, because the writeback is unsupported. */ + RADV_CMD_FLAG_WB_L2 = 1 << 4, /* Framebuffer caches */ - RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5, - RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6, - RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7, - RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8, + RADV_CMD_FLAG_FLUSH_AND_INV_CB_META = 1 << 5, + RADV_CMD_FLAG_FLUSH_AND_INV_DB_META = 1 << 6, + RADV_CMD_FLAG_FLUSH_AND_INV_DB = 1 << 7, + RADV_CMD_FLAG_FLUSH_AND_INV_CB = 1 << 8, /* Engine synchronization. */ - RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9, - RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10, - RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11, - RADV_CMD_FLAG_VGT_FLUSH = 1 << 12, + RADV_CMD_FLAG_VS_PARTIAL_FLUSH = 1 << 9, + RADV_CMD_FLAG_PS_PARTIAL_FLUSH = 1 << 10, + RADV_CMD_FLAG_CS_PARTIAL_FLUSH = 1 << 11, + RADV_CMD_FLAG_VGT_FLUSH = 1 << 12, /* Pipeline query controls. */ - RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13, - RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14, - RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15, + RADV_CMD_FLAG_START_PIPELINE_STATS = 1 << 13, + RADV_CMD_FLAG_STOP_PIPELINE_STATS = 1 << 14, + RADV_CMD_FLAG_VGT_STREAMOUT_SYNC = 1 << 15, RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER = (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META | |