diff options
| author | Samuel Pitoiset <[email protected]> | 2018-05-16 17:40:47 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-05-22 15:53:22 +0200 |
| commit | 36a4d6d08164344cbb4766944b3c45b2b223cf22 (patch) | |
| tree | ea2806dcef25b765ba1521488f0ae4d5c50509f8 /src/amd/vulkan/radv_private.h | |
| parent | b654ef5808e12a877f4645cf1394f56f954d0a50 (diff) | |
radv: add support for 32-bit pointers in user data SGPRs
We still use 64-bit GPU pointers for all ring buffers because
llvm.amdgcn.implicit.buffer.ptr doesn't seem to support 32-bit
GPU pointers for now. This can be improved later anyways.
Vega10:
Totals from affected shaders:
SGPRS: 1008722 -> 1026710 (1.78 %)
VGPRS: 706580 -> 707136 (0.08 %)
Spilled SGPRs: 22555 -> 22209 (-1.53 %)
Spilled VGPRs: 75 -> 75 (0.00 %)
Code Size: 34819208 -> 35202140 (1.10 %) bytes
Max Waves: 175423 -> 175086 (-0.19 %)
Polaris10:
Totals from affected shaders:
SGPRS: 1029849 -> 1036517 (0.65 %)
VGPRS: 709984 -> 708872 (-0.16 %)
Spilled SGPRs: 22672 -> 22309 (-1.60 %)
Spilled VGPRs: 82 -> 66 (-19.51 %)
Scratch size: 76 -> 60 (-21.05 %) dwords per thread
Code Size: 34915336 -> 35309752 (1.13 %) bytes
Max Waves: 151221 -> 151677 (0.30 %)
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index adfd75c2a87..e2fa58d8d1e 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -57,6 +57,7 @@ #include "ac_nir_to_llvm.h" #include "ac_gpu_info.h" #include "ac_surface.h" +#include "ac_llvm_build.h" #include "radv_descriptor_set.h" #include "radv_extensions.h" #include "radv_cs.h" @@ -1130,12 +1131,21 @@ bool radv_get_memory_fd(struct radv_device *device, int *pFD); static inline void -radv_emit_shader_pointer(struct radeon_winsys_cs *cs, - uint32_t sh_offset, uint64_t va) +radv_emit_shader_pointer(struct radv_device *device, + struct radeon_winsys_cs *cs, + uint32_t sh_offset, uint64_t va, bool global) { - radeon_set_sh_reg_seq(cs, sh_offset, 2); + bool use_32bit_pointers = HAVE_32BIT_POINTERS && !global; + + radeon_set_sh_reg_seq(cs, sh_offset, use_32bit_pointers ? 1 : 2); radeon_emit(cs, va); - radeon_emit(cs, va >> 32); + + if (use_32bit_pointers) { + assert(va == 0 || + (va >> 32) == device->physical_device->rad_info.address32_hi); + } else { + radeon_emit(cs, va >> 32); + } } static inline struct radv_descriptor_state * |