diff options
| author | Samuel Pitoiset <[email protected]> | 2018-02-28 20:28:53 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-03-01 09:53:40 +0100 |
| commit | c27f5419f6f6aa6d51b44a99b6738fba70873604 (patch) | |
| tree | a9496986edbbbd38708ed3b51b88b6481911b9db /src/amd/vulkan/radv_private.h | |
| parent | 2fe07933bd5385f731b490ba22ee2086bfccfe63 (diff) | |
radv: only emit cache flushes when the pool size is large enough
This is an optimization which reduces the number of flushes for
small pool buffers.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_private.h')
| -rw-r--r-- | src/amd/vulkan/radv_private.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 752b6a75922..0f8ddb2e106 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -95,6 +95,12 @@ typedef uint32_t xcb_window_t; #define NUM_DEPTH_CLEAR_PIPELINES 3 +/* + * This is the point we switch from using CP to compute shader + * for certain buffer operations. + */ +#define RADV_BUFFER_OPS_CS_THRESHOLD 4096 + enum radv_mem_heap { RADV_MEM_HEAP_VRAM, RADV_MEM_HEAP_VRAM_CPU_ACCESS, |