diff options
| author | Timothy Arceri <[email protected]> | 2018-10-18 09:42:17 +1100 |
|---|---|---|
| committer | Timothy Arceri <[email protected]> | 2018-10-18 15:04:09 +1100 |
| commit | 06675711e713e7ccd66aa076a6ba116286130474 (patch) | |
| tree | 6fdb82d52cb0060e484d359244d4ec0ecd9a599e /src/amd/vulkan/radv_pipeline.c | |
| parent | 9d5b106b2efbd5a4bbbe54a5a00c8cebd642d960 (diff) | |
radv: use nir_opt_find_array_copies()
Totals from affected shaders:
SGPRS: 1112 -> 1112 (0.00 %)
VGPRS: 1492 -> 1196 (-19.84 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 112172 -> 101316 (-9.68 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 93 -> 98 (5.38 %)
Wait states: 0 -> 0 (0.00 %)
All affected shaders are from "Batman: Arkham City" over DXVK.
The pass detects that the temporary array created by DXVK for
storing TCS inputs is a copy of the input arrays and allows
us to avoid copying all of the input data and then indirecting
on it with if-ladders, instead we just do indirect indexing.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e1d665d0ac7..8d15a048bbf 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1808,13 +1808,13 @@ radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders) ac_lower_indirect_derefs(ordered_shaders[i], pipeline->device->physical_device->rad_info.chip_class); } - radv_optimize_nir(ordered_shaders[i], false); + radv_optimize_nir(ordered_shaders[i], false, false); if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) { ac_lower_indirect_derefs(ordered_shaders[i - 1], pipeline->device->physical_device->rad_info.chip_class); } - radv_optimize_nir(ordered_shaders[i - 1], false); + radv_optimize_nir(ordered_shaders[i - 1], false, false); } } } @@ -2073,7 +2073,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline, if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)) { nir_lower_io_to_scalar_early(nir[i], mask); - radv_optimize_nir(nir[i], false); + radv_optimize_nir(nir[i], false, false); } } } |