diff options
| author | Dave Airlie <[email protected]> | 2018-02-19 05:53:33 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-03-16 05:22:32 +0000 |
| commit | f343d11ae7ff9fec6736a3933ff6272cba824f74 (patch) | |
| tree | df6e046dfae97c2919b30bab0495fcecb8464766 /src/amd/vulkan/radv_pipeline.c | |
| parent | d89b16b7b9c3de8b7a7b896822f3893fdda4dbec (diff) | |
radv: drop ls_out_layout const.
We can precalculate input_vertex_size at compile time.
Reviewed-by: Samuel Pitoiset <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index e02e06505e4..6d175169343 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2632,16 +2632,6 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, tess->offchip_layout); } - - loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX, AC_UD_VS_LS_TCS_IN_LAYOUT); - if (loc->sgpr_idx != -1) { - uint32_t base_reg = pipeline->user_data_0[MESA_SHADER_VERTEX]; - assert(loc->num_sgprs == 1); - assert(!loc->indirect); - - radeon_set_sh_reg(cs, base_reg + loc->sgpr_idx * 4, - tess->tcs_in_layout); - } } static void |