diff options
| author | Dave Airlie <[email protected]> | 2018-02-19 04:59:53 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2018-02-21 00:01:36 +0000 |
| commit | baa0feb73d0c011f3a2b29626244d3936532361e (patch) | |
| tree | 761ebfd0e259411628e2f457dfbe82107b443854 /src/amd/vulkan/radv_pipeline.c | |
| parent | 952222ddd423bce3b6e836f3ae305cbad0622e22 (diff) | |
radv: don't send num_tcs_input_cp to sgprs.
We never use it in the shaders.
Reviewed-by: Samuel Pitoiset <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a2dec0e3bdd..9990a3e863c 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -68,7 +68,6 @@ struct radv_tessellation_state { uint32_t offchip_layout; unsigned num_patches; unsigned lds_size; - unsigned num_tcs_input_cp; uint32_t tf_param; }; @@ -1397,7 +1396,6 @@ calculate_tess_state(struct radv_pipeline *pipeline, S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) | S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp); tess.num_patches = num_patches; - tess.num_tcs_input_cp = num_tcs_input_cp; struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline); unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0; @@ -2621,8 +2619,7 @@ radv_pipeline_generate_tess_shaders(struct radeon_winsys_cs *cs, radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4); radeon_emit(cs, tess->offchip_layout); radeon_emit(cs, tess->tcs_out_offsets); - radeon_emit(cs, tess->tcs_out_layout | - tess->num_tcs_input_cp << 26); + radeon_emit(cs, tess->tcs_out_layout); radeon_emit(cs, tess->tcs_in_layout); } |