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authorSamuel Pitoiset <[email protected]>2018-04-04 10:55:43 +0200
committerSamuel Pitoiset <[email protected]>2018-04-04 13:32:00 +0200
commitb8c06a961c903cfae48bb3dc2e64a51796bd8a5a (patch)
treede417aa94d7bb24196e1d266e8143bc971d01db7 /src/amd/vulkan/radv_pipeline.c
parentab147cba77006cdbaf774d7a627c594be8980209 (diff)
radv: don't use the SPI barrier management bug workaround
Ported from RadeonSI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
-rw-r--r--src/amd/vulkan/radv_pipeline.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5a44efb78b3..89a643a1b10 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1274,6 +1274,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
static void si_multiwave_lds_size_workaround(struct radv_device *device,
unsigned *lds_size)
{
+ /* If tessellation is all offchip and on-chip GS isn't used, this
+ * workaround is not needed.
+ */
+ return;
+
/* SPI barrier management bug:
* Make sure we have at least 4k of LDS in use to avoid the bug.
* It applies to workgroup sizes of more than one wavefront.