diff options
author | Dave Airlie <[email protected]> | 2018-02-20 13:30:14 +1000 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2018-03-16 05:23:12 +0000 |
commit | 9188bd78d7e2754f36ad66db3fab80c8ee9f5093 (patch) | |
tree | 2a6650558ce0e2746ddd1c5b7f2b8658301cdaf7 /src/amd/vulkan/radv_pipeline.c | |
parent | 384aced65e7768f7bba1a6159c6730efdd514d6c (diff) |
radv: migrate lds size calculations to shader gen.
This moves the lds_size calcs into the shader so we have all
the size stuff in one file.
Reviewed-by: Samuel Pitoiset <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
-rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 29 |
1 files changed, 4 insertions, 25 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 771bc2e4080..a4836abf7f1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1306,38 +1306,17 @@ static struct radv_tessellation_state calculate_tess_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - unsigned num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; - unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs; - unsigned num_tcs_patch_outputs; - unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size; - unsigned input_patch_size, output_patch_size, output_patch0_offset; + unsigned num_tcs_input_cp; + unsigned num_tcs_output_cp; unsigned lds_size; unsigned num_patches; struct radv_tessellation_state tess = {0}; - /* This calculates how shader inputs and outputs among VS, TCS, and TES - * are laid out in LDS. */ - num_tcs_inputs = util_last_bit64(radv_get_vertex_shader(pipeline)->info.info.vs.ls_outputs_written); - num_tcs_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written); //tcs->outputs_written + num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints; num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT - num_tcs_patch_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.patch_outputs_written); - - /* Ensure that we only need one wave per SIMD so we don't need to check - * resource usage. Also ensures that the number of tcs in and out - * vertices per threadgroup are at most 256. - */ - input_vertex_size = num_tcs_inputs * 16; - output_vertex_size = num_tcs_outputs * 16; - - input_patch_size = num_tcs_input_cp * input_vertex_size; - - pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size; - output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16; - num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches; - output_patch0_offset = input_patch_size * num_patches; - lds_size = output_patch0_offset + output_patch_size * num_patches; + lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size; if (pipeline->device->physical_device->rad_info.chip_class >= CIK) { assert(lds_size <= 65536); |