diff options
| author | Dave Airlie <[email protected]> | 2017-11-06 02:00:34 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-11-13 07:16:53 +0000 |
| commit | 031e591923fad7792a4e2e0522cf63a3ff62bc69 (patch) | |
| tree | 6bdd490bec89281275c396505a8020b6f8b1e7e1 /src/amd/vulkan/radv_pipeline.c | |
| parent | 4a9aad96aa6d18d5afc20727b1791501cfb7cb48 (diff) | |
radv: move calculating vs out info regs into pipeline.
This moves some calculations of register values into the pipeline
construction, it saves looking at outinfo in the cmd buffer emit.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index f62c8b4be88..d74e05d6c82 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1545,7 +1545,7 @@ static void calculate_vgt_gs_mode(struct radv_pipeline *pipeline) } } -static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline) +static void calculate_vs_outinfo(struct radv_pipeline *pipeline) { struct ac_vs_output_info *outinfo = get_vs_output_info(pipeline); @@ -1557,7 +1557,7 @@ static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline) bool misc_vec_ena = outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_viewport_index; - pipeline->graphics.pa_cl_vs_out_cntl = + pipeline->graphics.vs.pa_cl_vs_out_cntl = S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) | S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) | S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) | @@ -1568,6 +1568,21 @@ static void calculate_pa_cl_vs_out_cntl(struct radv_pipeline *pipeline) cull_dist_mask << 8 | clip_dist_mask; + pipeline->graphics.vs.spi_shader_pos_format = + S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) | + S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ? + V_02870C_SPI_SHADER_4COMP : + V_02870C_SPI_SHADER_NONE) | + S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ? + V_02870C_SPI_SHADER_4COMP : + V_02870C_SPI_SHADER_NONE) | + S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ? + V_02870C_SPI_SHADER_4COMP : + V_02870C_SPI_SHADER_NONE); + + pipeline->graphics.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(MAX2(1, outinfo->param_exports) - 1); + /* only emitted on pre-VI */ + pipeline->graphics.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(outinfo->writes_viewport_index); } static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade) @@ -2093,7 +2108,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline, V_028710_SPI_SHADER_ZERO; calculate_vgt_gs_mode(pipeline); - calculate_pa_cl_vs_out_cntl(pipeline); + calculate_vs_outinfo(pipeline); calculate_ps_inputs(pipeline); for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) { |