diff options
author | Bas Nieuwenhuizen <[email protected]> | 2018-01-16 14:32:35 +0100 |
---|---|---|
committer | Bas Nieuwenhuizen <[email protected]> | 2018-01-30 22:00:17 +0100 |
commit | 7c366bc15277dda9a3003abbb83a58cd32a0f980 (patch) | |
tree | 8661f81acccd28471533aec298feda71cb0cf6d4 /src/amd/vulkan/radv_pipeline.c | |
parent | 0a89784bcc988d602bbe8b310aca8c54ef03d954 (diff) |
radv: Determine unneeded dynamic states.
Which avoids setting or emitting them.
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
-rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 61 |
1 files changed, 45 insertions, 16 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 589e49a813d..6bdb1160cb2 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -1031,15 +1031,48 @@ static unsigned radv_dynamic_state_mask(VkDynamicState state) } } +static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo) +{ + uint32_t states = RADV_DYNAMIC_ALL; + + /* If rasterization is disabled we do not care about any of the dynamic states, + * since they are all rasterization related only. */ + if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable) + return 0; + + if (!pCreateInfo->pRasterizationState->depthBiasEnable) + states &= ~RADV_DYNAMIC_DEPTH_BIAS; + + if (!pCreateInfo->pDepthStencilState || + !pCreateInfo->pDepthStencilState->depthBoundsTestEnable) + states &= ~RADV_DYNAMIC_DEPTH_BOUNDS; + + if (!pCreateInfo->pDepthStencilState || + !pCreateInfo->pDepthStencilState->stencilTestEnable) + states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK | + RADV_DYNAMIC_STENCIL_WRITE_MASK | + RADV_DYNAMIC_STENCIL_REFERENCE); + + if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT)) + states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE; + + /* TODO: blend constants & line width. */ + + return states; +} + + static void radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { - uint32_t states = RADV_DYNAMIC_ALL; + uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo); + uint32_t states = needed_states; RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass); struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass]; pipeline->dynamic_state = default_dynamic_state; + pipeline->graphics.needed_dynamic_state = needed_states; if (pCreateInfo->pDynamicState) { /* Remove all of the states that are marked as dynamic */ @@ -1050,26 +1083,23 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, struct radv_dynamic_state *dynamic = &pipeline->dynamic_state; - /* Section 9.2 of the Vulkan 1.0.15 spec says: - * - * pViewportState is [...] NULL if the pipeline - * has rasterization disabled. - */ - if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) { + if (needed_states & RADV_DYNAMIC_VIEWPORT) { assert(pCreateInfo->pViewportState); dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount; if (states & RADV_DYNAMIC_VIEWPORT) { typed_memcpy(dynamic->viewport.viewports, - pCreateInfo->pViewportState->pViewports, - pCreateInfo->pViewportState->viewportCount); + pCreateInfo->pViewportState->pViewports, + pCreateInfo->pViewportState->viewportCount); } + } + if (needed_states & RADV_DYNAMIC_SCISSOR) { dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount; if (states & RADV_DYNAMIC_SCISSOR) { typed_memcpy(dynamic->scissor.scissors, - pCreateInfo->pViewportState->pScissors, - pCreateInfo->pViewportState->scissorCount); + pCreateInfo->pViewportState->pScissors, + pCreateInfo->pViewportState->scissorCount); } } @@ -1120,7 +1150,7 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, * disabled or if the subpass of the render pass the pipeline is created * against does not use a depth/stencil attachment. */ - if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable && + if (needed_states && subpass->depth_stencil_attachment.attachment != VK_ATTACHMENT_UNUSED) { assert(pCreateInfo->pDepthStencilState); @@ -1155,7 +1185,7 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info = vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT); - if (discard_rectangle_info) { + if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) { dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount; typed_memcpy(dynamic->discard_rectangle.rectangles, discard_rectangle_info->pDiscardRectangles, @@ -1181,8 +1211,6 @@ radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline, } pipeline->graphics.pa_sc_cliprect_rule = mask; } else { - states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE; - /* Allow from all rectangle combinations */ pipeline->graphics.pa_sc_cliprect_rule = 0xffff; } @@ -2441,7 +2469,6 @@ radv_pipeline_init(struct radv_pipeline *pipeline, pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout); assert(pipeline->layout); - radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra); const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, }; @@ -2476,6 +2503,8 @@ radv_pipeline_init(struct radv_pipeline *pipeline, /* prim vertex count will need TESS changes */ pipeline->graphics.prim_vertex_count = prim_size_table[pipeline->graphics.prim]; + radv_pipeline_init_dynamic_state(pipeline, pCreateInfo); + /* Ensure that some export memory is always allocated, for two reasons: * * 1) Correctness: The hardware ignores the EXEC mask if no export |