diff options
| author | Timur Kristóf <[email protected]> | 2019-09-13 15:53:09 +0200 |
|---|---|---|
| committer | Connor Abbott <[email protected]> | 2019-09-26 13:36:49 +0000 |
| commit | 83eebdb5078872fbf0ff67cac6b08823d6a1293c (patch) | |
| tree | 43540c39a080e34c5403661be3b4e2066be16b6b /src/amd/vulkan/radv_pipeline.c | |
| parent | 7bde4ddaf723a604999feefaee30ed8aae35a830 (diff) | |
radv: Set shared VGPR count in radv_postprocess_config.
This commit allows RADV to set the shared VGPR count according to
the shader config.
Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_pipeline.c')
| -rw-r--r-- | src/amd/vulkan/radv_pipeline.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index c107d551138..ddf94625972 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4831,8 +4831,8 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline) unsigned max_waves_per_sh = 0; uint64_t va; - pipeline->cs.buf = malloc(20 * 4); - pipeline->cs.max_dw = 20; + pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20; + pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4); compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE]; va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset; @@ -4844,6 +4844,9 @@ radv_compute_generate_pm4(struct radv_pipeline *pipeline) radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2); radeon_emit(&pipeline->cs, compute_shader->config.rsrc1); radeon_emit(&pipeline->cs, compute_shader->config.rsrc2); + if (device->physical_device->rad_info.chip_class >= GFX10) { + radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3); + } radeon_set_sh_reg(&pipeline->cs, R_00B860_COMPUTE_TMPRING_SIZE, S_00B860_WAVES(pipeline->max_waves) | |