diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2018-07-16 20:51:26 +0200 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2019-04-25 19:56:20 +0000 |
| commit | 42d159f2766421b7a2858aa8de7762e8dfc9257f (patch) | |
| tree | c2a5696af233c93b7d3b7abc954835b30f05bd87 /src/amd/vulkan/radv_meta_clear.c | |
| parent | d3225e533fe3ac90cdded81e4f7df55082bc387e (diff) | |
radv: Add multiple planes to images.
No functional changes. This temporarily uses plane 0 for
everything.
Long term plan is that only single plane images get to use
metadata like htile/dcc/cmask/fmask.
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_meta_clear.c')
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 101ef4344f4..40ecfe001d1 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -869,7 +869,7 @@ radv_get_htile_fast_clear_value(const struct radv_image *image, { uint32_t clear_value; - if (!image->surface.has_stencil) { + if (!image->planes[0].surface.has_stencil) { clear_value = value.depth ? 0xfffffff0 : 0; } else { clear_value = value.depth ? 0xfffc0000 : 0; @@ -883,7 +883,7 @@ radv_get_htile_mask(const struct radv_image *image, VkImageAspectFlags aspects) { uint32_t mask = 0; - if (!image->surface.has_stencil) { + if (!image->planes[0].surface.has_stencil) { /* All the HTILE buffer is used when there is no stencil. */ mask = UINT32_MAX; } else { @@ -1034,13 +1034,13 @@ radv_fast_clear_depth(struct radv_cmd_buffer *cmd_buffer, /* Clear the whole HTILE buffer. */ flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo, iview->image->offset + iview->image->htile_offset, - iview->image->surface.htile_size, clear_word); + iview->image->planes[0].surface.htile_size, clear_word); } else { /* Only clear depth or stencil bytes in the HTILE buffer. */ assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9); flush_bits = clear_htile_mask(cmd_buffer, iview->image->bo, iview->image->offset + iview->image->htile_offset, - iview->image->surface.htile_size, clear_word, + iview->image->planes[0].surface.htile_size, clear_word, htile_mask); } @@ -1341,7 +1341,7 @@ radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer, return radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->dcc_offset, - image->surface.dcc_size, value); + image->planes[0].surface.dcc_size, value); } static void vi_get_fast_clear_parameters(VkFormat format, |