diff options
| author | Samuel Pitoiset <[email protected]> | 2017-10-26 18:03:23 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-10-27 13:47:03 +0200 |
| commit | 0d61109bb75333b3e80fda69cbc5b75b0f3f9233 (patch) | |
| tree | 3c39d9a62be039f3e8d800f02b51aa26fc050a67 /src/amd/vulkan/radv_meta_clear.c | |
| parent | 4b9421d45da41955947f4c75be033ec1bc1d18f5 (diff) | |
radv: make radv_fill_buffer() return the needed flush bits
Only needed when the CS path is used.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_meta_clear.c')
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 50 |
1 files changed, 22 insertions, 28 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index dd0c1a01d32..7b6ab4a9b72 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -678,7 +678,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview = fb->attachments[pass_att].attachment; VkClearDepthStencilValue clear_value = clear_att->clearValue.depthStencil; VkImageAspectFlags aspects = clear_att->aspectMask; - uint32_t clear_word; + uint32_t clear_word, flush_bits; if (!iview->image->surface.htile_size) return false; @@ -730,20 +730,17 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer, cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; - radv_fill_buffer(cmd_buffer, iview->image->bo, - iview->image->offset + iview->image->htile_offset, - iview->image->surface.htile_size, clear_word); - + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo, + iview->image->offset + iview->image->htile_offset, + iview->image->surface.htile_size, clear_word); radv_set_depth_clear_regs(cmd_buffer, iview->image, clear_value, aspects); - if (post_flush) - *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; - else - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; + if (post_flush) { + *post_flush |= flush_bits; + } else { + cmd_buffer->state.flush_bits |= flush_bits; + } + return true; fail: return false; @@ -952,7 +949,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, const struct radv_framebuffer *fb = cmd_buffer->state.framebuffer; const struct radv_image_view *iview = fb->attachments[pass_att].attachment; VkClearColorValue clear_value = clear_att->clearValue.color; - uint32_t clear_color[2]; + uint32_t clear_color[2], flush_bits; bool ret; if (!iview->image->cmask.size && !iview->image->surface.dcc_size) @@ -1021,25 +1018,22 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, &clear_value, &reset_value, &can_avoid_fast_clear_elim); - radv_fill_buffer(cmd_buffer, iview->image->bo, - iview->image->offset + iview->image->dcc_offset, - iview->image->surface.dcc_size, reset_value); + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo, + iview->image->offset + iview->image->dcc_offset, + iview->image->surface.dcc_size, reset_value); radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image, !can_avoid_fast_clear_elim); } else { - radv_fill_buffer(cmd_buffer, iview->image->bo, - iview->image->offset + iview->image->cmask.offset, - iview->image->cmask.size, 0); + flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo, + iview->image->offset + iview->image->cmask.offset, + iview->image->cmask.size, 0); } - if (post_flush) - *post_flush |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; - else - cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2; + if (post_flush) { + *post_flush |= flush_bits; + } else { + cmd_buffer->state.flush_bits |= flush_bits; + } radv_set_color_clear_regs(cmd_buffer, iview->image, subpass_att, clear_color); |