diff options
| author | Samuel Pitoiset <[email protected]> | 2018-04-17 16:05:14 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-04-19 09:10:45 +0200 |
| commit | 255506c4e04bfa5490d98a748aa248189a213ad6 (patch) | |
| tree | 2811e5b1f320502bdc61e8476c14f6b8e197937f /src/amd/vulkan/radv_meta_clear.c | |
| parent | 796b6f4aab46924f9954c9b2a9821b4706618cab (diff) | |
radv: implement fast color clear for DCC with MSAA
When DCC is enabled with MSAA textures, CMASK should be
cleared to 0xCCCCCCCC.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_meta_clear.c')
| -rw-r--r-- | src/amd/vulkan/radv_meta_clear.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c index 016c1ee296e..86e0bc17ed8 100644 --- a/src/amd/vulkan/radv_meta_clear.c +++ b/src/amd/vulkan/radv_meta_clear.c @@ -1054,14 +1054,29 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer, if (radv_image_has_dcc(iview->image)) { uint32_t reset_value; bool can_avoid_fast_clear_elim; + bool need_decompress_pass = false; + vi_get_fast_clear_parameters(iview->image->vk_format, &clear_value, &reset_value, &can_avoid_fast_clear_elim); + if (iview->image->info.samples > 1) { + /* DCC fast clear with MSAA should clear CMASK. */ + assert(radv_image_has_cmask(iview->image)); + + flush_bits = radv_clear_cmask(cmd_buffer, iview->image, + cmask_clear_value); + + need_decompress_pass = true; + } + + if (!can_avoid_fast_clear_elim) + need_decompress_pass = true; + flush_bits = radv_clear_dcc(cmd_buffer, iview->image, reset_value); radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image, - !can_avoid_fast_clear_elim); + need_decompress_pass); } else { flush_bits = radv_clear_cmask(cmd_buffer, iview->image, cmask_clear_value); |