diff options
| author | Samuel Pitoiset <[email protected]> | 2017-09-28 10:24:09 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2017-10-02 11:56:20 +0200 |
| commit | db2e68b66b766be289a58b74add9af392b304eca (patch) | |
| tree | ddfdaf020621ba58f143ee4304703f73131f0ce5 /src/amd/vulkan/radv_image.c | |
| parent | 457306fa4c747db5a8f19eb6561b252ddcd211cf (diff) | |
radv: add radv_vi_dcc_enabled() helper
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index e28aba060b2..35c58f45ab5 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -251,7 +251,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device, if (chip_class >= VI) { state[6] &= C_008F28_COMPRESSION_EN; state[7] = 0; - if (image->surface.dcc_size && first_level < image->surface.num_dcc_levels) { + if (radv_vi_dcc_enabled(image, first_level)) { meta_va = gpu_address + image->dcc_offset; if (chip_class <= VI) meta_va += base_level_info->dcc_offset; |