diff options
author | Dave Airlie <[email protected]> | 2017-03-02 21:39:10 +0000 |
---|---|---|
committer | Dave Airlie <[email protected]> | 2017-07-17 01:44:43 +0100 |
commit | 9ee67467c9ea592340aee10a55ba54d7266ff0a9 (patch) | |
tree | 4588211428eb7a5f369bd0ac3629f32d34863d8a /src/amd/vulkan/radv_image.c | |
parent | 8eed291c2c4bfaddf256dcdb10bfa95bfe2b7c58 (diff) |
radv: predicate cmask eliminate when using DCC.
When using DCC some clear values don't require a cmask eliminate
step. This patch adds support for black and black with alpha 1,
there are other values, but I don't have access to a comprehensive list.
This works by setting the cmask eliminate predicate when doing the
fast clear, and later when doing the cmask elimination making sure
the draws are predicated.
This increases the fps on Sascha Willems deferred.
Tonga: 580fps->670fps on a Tonga PRO card.
Polaris 730->850fps
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
-rw-r--r-- | src/amd/vulkan/radv_image.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index a8af4fd6d68..9e54b95ac3f 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -712,12 +712,16 @@ static void radv_image_alloc_cmask(struct radv_device *device, struct radv_image *image) { + uint32_t clear_value_size = 0; radv_image_get_cmask_info(device, image, &image->cmask); image->cmask.offset = align64(image->size, image->cmask.alignment); /* + 8 for storing the clear values */ - image->clear_value_offset = image->cmask.offset + image->cmask.size; - image->size = image->cmask.offset + image->cmask.size + 8; + if (!image->clear_value_offset) { + image->clear_value_offset = image->cmask.offset + image->cmask.size; + clear_value_size = 8; + } + image->size = image->cmask.offset + image->cmask.size + clear_value_size; image->alignment = MAX2(image->alignment, image->cmask.alignment); } @@ -726,9 +730,10 @@ radv_image_alloc_dcc(struct radv_device *device, struct radv_image *image) { image->dcc_offset = align64(image->size, image->surface.dcc_alignment); - /* + 8 for storing the clear values */ + /* + 16 for storing the clear values + dcc pred */ image->clear_value_offset = image->dcc_offset + image->surface.dcc_size; - image->size = image->dcc_offset + image->surface.dcc_size + 8; + image->dcc_pred_offset = image->clear_value_offset + 8; + image->size = image->dcc_offset + image->surface.dcc_size + 16; image->alignment = MAX2(image->alignment, image->surface.dcc_alignment); } |