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authorSamuel Pitoiset <[email protected]>2018-04-06 16:00:08 +0200
committerSamuel Pitoiset <[email protected]>2018-04-09 11:21:14 +0200
commited41e776d03d27d2874f9b02e00bbd1f2226528f (patch)
treed0df38cc2ed2acf670513affc106b9db6d527470 /src/amd/vulkan/radv_image.c
parente213f199079365ff03a7012b2b57f1d47843d507 (diff)
radv: clean up radv_vi_dcc_enabled()
And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
-rw-r--r--src/amd/vulkan/radv_image.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 56b9ba1cdaf..1a8352fea27 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -294,7 +294,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
if (chip_class >= VI) {
state[6] &= C_008F28_COMPRESSION_EN;
state[7] = 0;
- if (!is_storage_image && radv_vi_dcc_enabled(image, first_level)) {
+ if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
meta_va += base_level_info->dcc_offset;