diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-23 10:48:20 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-26 15:56:51 +0200 |
| commit | 9db0dc6b8e18d7cfd60b900da72264f7a5e39484 (patch) | |
| tree | b0d761bceb7aaa988fca291ac0d38985513227e5 /src/amd/vulkan/radv_image.c | |
| parent | 76812339f7cf4c742cec5b65bf3598dd965cfc53 (diff) | |
radv: allocate metadata space for mipmapped depth/stencil images
For each mipmaps, the driver will store the clear values (8-bytes)
and the TC-compat zrange value (4-bytes).
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
| -rw-r--r-- | src/amd/vulkan/radv_image.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 34eb672d6ac..f0c9fd77cf6 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -1157,7 +1157,7 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image) /* + 8 for storing the clear values */ image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size; - image->size = image->clear_value_offset + 8; + image->size = image->clear_value_offset + image->info.levels * 8; if (radv_image_is_tc_compat_htile(image) && device->physical_device->has_tc_compat_zrange_bug) { /* Metadata for the TC-compatible HTILE hardware bug which @@ -1165,7 +1165,7 @@ radv_image_alloc_htile(struct radv_device *device, struct radv_image *image) * fast depth clears to 0.0f. */ image->tc_compat_zrange_offset = image->size; - image->size = image->tc_compat_zrange_offset + 4; + image->size = image->tc_compat_zrange_offset + image->info.levels * 4; } image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment); } |