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authorDave Airlie <[email protected]>2017-08-04 06:54:15 +0100
committerDave Airlie <[email protected]>2017-08-07 00:08:43 +0100
commit1e696b962b7207bb87cf9fc91e2a9de9a3becfba (patch)
tree1c142ad9ce85b5ccdd415d59f0a4774795360222 /src/amd/vulkan/radv_image.c
parent3f389f75b6e9b55467aca681af09b83998ee0e46 (diff)
radv: add separate fmask tile swizzle counter.
This mirrors what Marek has done for radeonsi, and uses a separate counter to handle the fmask surface for MSAA MRTs. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_image.c')
-rw-r--r--src/amd/vulkan/radv_image.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c27c3b6ddc6..1ccd4a463f0 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -484,7 +484,7 @@ si_make_texture_descriptor(struct radv_device *device,
fmask_state[0] = va >> 8;
if (device->physical_device->rad_info.chip_class < GFX9)
- fmask_state[0] |= image->surface.tile_swizzle;
+ fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
@@ -616,6 +616,8 @@ radv_image_get_fmask_info(struct radv_device *device,
info.samples = 1;
fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
+ info.surf_index = &device->fmask_mrt_offset_counter;
+
/* Force 2D tiling if it wasn't set. This may occur when creating
* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
* destination buffer must have an FMASK too. */
@@ -644,6 +646,7 @@ radv_image_get_fmask_info(struct radv_device *device,
out->tile_mode_index = fmask.u.legacy.tiling_index[0];
out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
out->bank_height = fmask.u.legacy.bankh;
+ out->tile_swizzle = fmask.tile_swizzle;
out->alignment = MAX2(256, fmask.surf_alignment);
out->size = fmask.surf_size;
}