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| author | Topi Pohjolainen <[email protected]> | 2018-10-16 07:56:51 -0400 |
|---|---|---|
| committer | Topi Pohjolainen <[email protected]> | 2018-10-17 21:19:57 +0300 |
| commit | a11cafbd7af1980a277ffbca00acb0b1f7f25309 (patch) | |
| tree | b421f335936202c966a23ab38fd352d766d3cc76 /src/amd/vulkan/radv_extensions.py | |
| parent | a9475d9337a391f5818b3bd799877098d7cbd79b (diff) | |
intel/compiler/icl: Use invocation id bits 22:16 instead of 23:17
Identifier bits in the dispatch header have changed. See Bspec:
SINGLE_PATCH Payload:
3D Pipeline Stages - 3D Pipeline Geometry -
Hull Shader (HS) Stage IVB+ - Payloads IVB+
Fixes: KHR-GL46.tessellation_shader.tessellation_shader_tc_barriers.barrier_guarded_read_write_calls
Reviewed-by: Anuj Phogat <[email protected]>
Signed-off-by: Topi Pohjolainen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_extensions.py')
0 files changed, 0 insertions, 0 deletions