diff options
| author | Samuel Pitoiset <[email protected]> | 2018-07-10 16:13:38 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-07-12 11:08:40 +0200 |
| commit | 6248fbe5e42ef2a620b4c3793af2b809fab6f169 (patch) | |
| tree | df2b4e2031c5b866130abe0245da7e7f3ef285a2 /src/amd/vulkan/radv_device.c | |
| parent | 501d0edeca321637b20a0ad1b9d476e6919131c3 (diff) | |
radv: get rid of buffer object priorities
We mostly use the same priority for all buffer objects, so
I don't think that matter much. This should reduce CPU
overhead a little bit.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_device.c')
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 1c0a50c82fa..8274b6ea096 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -1928,10 +1928,10 @@ radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs, return; if (esgs_ring_bo) - radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo); if (gsvs_ring_bo) - radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo); if (queue->device->physical_device->rad_info.chip_class >= CIK) { radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2); @@ -1956,7 +1956,7 @@ radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs, tf_va = radv_buffer_get_va(tess_rings_bo); - radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo); if (queue->device->physical_device->rad_info.chip_class >= CIK) { radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE, @@ -1990,7 +1990,7 @@ radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs, scratch_va = radv_buffer_get_va(compute_scratch_bo); - radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo); radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); radeon_emit(cs, scratch_va); @@ -2010,7 +2010,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue, va = radv_buffer_get_va(descriptor_bo); - radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo); if (queue->device->physical_device->rad_info.chip_class >= GFX9) { uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0, @@ -2189,7 +2189,7 @@ radv_get_preamble_cs(struct radv_queue *queue, dest_cs[i] = cs; if (scratch_bo) - radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8); + radv_cs_add_buffer(queue->device->ws, cs, scratch_bo); if (descriptor_bo != queue->descriptor_bo) { uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo); |