radv: Don't use a virtual function for getting the buffer virtual address.

We are really not going to use a winsys which does not need to store
the va, so might as well store it in a standard field.

Not sure this helps perf much though, as most of the cost is in the
cache miss accessing the bo anyway, which we stil need to do.

Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>

1 files changed, 15 insertions, 15 deletions

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7bfdddf0eea..2067685c5ab 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1381,13 +1381,13 @@ fill_geom_tess_rings(struct radv_queue *queue,
 	uint32_t *desc = &map[4];
 
 	if (esgs_ring_bo)
-		esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
+		esgs_va = radv_buffer_get_va(esgs_ring_bo);
 	if (gsvs_ring_bo)
-		gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
+		gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
 	if (tess_factor_ring_bo)
-		tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
+		tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
 	if (tess_offchip_ring_bo)
-		tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
+		tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
 
 	/* stride 0, num records - size, add tid, swizzle, elsize4,
 	   index stride 64 */
@@ -1734,7 +1734,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
 			uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
 
 			if (scratch_bo) {
-				uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
+				uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
 				uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
 				                 S_008F04_SWIZZLE_ENABLE(1);
 				map[0] = scratch_va;
@@ -1772,7 +1772,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
 		}
 
 		if (tess_factor_ring_bo) {
-			uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
+			uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
 			if (queue->device->physical_device->rad_info.chip_class >= CIK) {
 				radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
 						       S_030938_SIZE(tess_factor_ring_size / 4));
@@ -1801,7 +1801,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
 			                   R_00B430_SPI_SHADER_USER_DATA_HS_0,
 			                   R_00B530_SPI_SHADER_USER_DATA_LS_0};
 
-			uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
+			uint64_t va = radv_buffer_get_va(descriptor_bo);
 
 			for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
 				radeon_set_sh_reg_seq(cs, regs[i], 2);
@@ -1811,7 +1811,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
 		}
 
 		if (compute_scratch_bo) {
-			uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
+			uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
 			uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
 			                 S_008F04_SWIZZLE_ENABLE(1);
 
@@ -2989,7 +2989,7 @@ radv_initialise_color_surface(struct radv_device *device,
 	/* Intensity is implemented as Red, so treat it that way. */
 	cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
 
-	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
+	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
 
 	cb->cb_color_base = va >> 8;
 
@@ -3041,11 +3041,11 @@ radv_initialise_color_surface(struct radv_device *device,
 	}
 
 	/* CMASK variables */
-	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
+	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
 	va += iview->image->cmask.offset;
 	cb->cb_color_cmask = va >> 8;
 
-	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
+	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
 	va += iview->image->dcc_offset;
 	cb->cb_dcc_base = va >> 8;
 	cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
@@ -3062,7 +3062,7 @@ radv_initialise_color_surface(struct radv_device *device,
 	}
 
 	if (iview->image->fmask.size) {
-		va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
+		va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
 		cb->cb_color_fmask = va >> 8;
 		cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
 	} else {
@@ -3207,7 +3207,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 	ds->db_htile_data_base = 0;
 	ds->db_htile_surface = 0;
 
-	va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
+	va = radv_buffer_get_va(iview->bo) + iview->image->offset;
 	s_offs = z_offs = va;
 
 	if (device->physical_device->rad_info.chip_class >= GFX9) {
@@ -3235,7 +3235,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 			if (!iview->image->surface.has_stencil)
 				/* Use all of the htile_buffer for depth if there's no stencil. */
 				ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
-			va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
+			va = radv_buffer_get_va(iview->bo) + iview->image->offset +
 				iview->image->htile_offset;
 			ds->db_htile_data_base = va >> 8;
 			ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
@@ -3299,7 +3299,7 @@ radv_initialise_ds_surface(struct radv_device *device,
 				/* Use all of the htile_buffer for depth if there's no stencil. */
 				ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
 
-			va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
+			va = radv_buffer_get_va(iview->bo) + iview->image->offset +
 				iview->image->htile_offset;
 			ds->db_htile_data_base = va >> 8;
 			ds->db_htile_surface = S_028ABC_FULL_CACHE(1);