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authorMatthew Nicholls <[email protected]>2018-01-29 16:26:18 +0000
committerEmil Velikov <[email protected]>2018-02-05 19:06:02 +0000
commit7eaa4049f11ececb06b0065611ea9161b3e501b0 (patch)
treec5d096ff1ae5ef331bbd90167967f65623b159b4 /src/amd/vulkan/radv_device.c
parent15ef35052c0df90b4dc54bd1e1f4005227311442 (diff)
radv: remove predication on cache flushes
This can lead to a situation where cache flushes could get conditionally disabled while still clearing the flush_bits, and thus flushes due to application pipeline barriers may never get executed. Fixes: a6c2001ace (radv: add support for cmd predication.) Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit ef272b161e05e8216f2d1f4df5023f3aed0ae4fa) [Emil Velikov: trivial conflicts] Signed-off-by: Emil Velikov <[email protected]> Conflicts: src/amd/vulkan/radv_cmd_buffer.c
Diffstat (limited to 'src/amd/vulkan/radv_device.c')
-rw-r--r--src/amd/vulkan/radv_device.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 2ce667fd212..aea723cfbcd 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1771,7 +1771,6 @@ radv_get_preamble_cs(struct radv_queue *queue,
if (i == 0) {
si_cs_emit_cache_flush(cs,
- false,
queue->device->physical_device->rad_info.chip_class,
NULL, 0,
queue->queue_family_index == RING_COMPUTE &&
@@ -1783,7 +1782,6 @@ radv_get_preamble_cs(struct radv_queue *queue,
RADV_CMD_FLAG_INV_GLOBAL_L2);
} else if (i == 1) {
si_cs_emit_cache_flush(cs,
- false,
queue->device->physical_device->rad_info.chip_class,
NULL, 0,
queue->queue_family_index == RING_COMPUTE &&