diff options
| author | Samuel Pitoiset <[email protected]> | 2019-06-25 17:57:45 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-06-25 18:38:37 +0200 |
| commit | 8ea7ee153649ac07c8418cc0d4aa5a4e123d19d1 (patch) | |
| tree | 05b4740f8d00e8de9c3d9b0ff0c896dab358b6dd /src/amd/vulkan/radv_device.c | |
| parent | 5411f470564f6f1c2a55d037103f051cbddd5623 (diff) | |
radv: rename and re-document cache flush flags
SMEM and VMEM caches are L0 on gfx10. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_device.c')
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index f12b8bde1f9..8d4964073cf 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2704,9 +2704,9 @@ radv_get_preamble_cs(struct radv_queue *queue, queue->device->physical_device->rad_info.chip_class >= GFX7, (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) | RADV_CMD_FLAG_INV_ICACHE | - RADV_CMD_FLAG_INV_SMEM_L1 | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_GLOBAL_L2 | + RADV_CMD_FLAG_INV_SCACHE | + RADV_CMD_FLAG_INV_VCACHE | + RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_START_PIPELINE_STATS, 0); } else if (i == 1) { si_cs_emit_cache_flush(cs, @@ -2715,9 +2715,9 @@ radv_get_preamble_cs(struct radv_queue *queue, queue->queue_family_index == RING_COMPUTE && queue->device->physical_device->rad_info.chip_class >= GFX7, RADV_CMD_FLAG_INV_ICACHE | - RADV_CMD_FLAG_INV_SMEM_L1 | - RADV_CMD_FLAG_INV_VMEM_L1 | - RADV_CMD_FLAG_INV_GLOBAL_L2 | + RADV_CMD_FLAG_INV_SCACHE | + RADV_CMD_FLAG_INV_VCACHE | + RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_START_PIPELINE_STATS, 0); } |