diff options
| author | Dave Airlie <[email protected]> | 2017-07-07 06:56:57 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-07-17 01:43:41 +0100 |
| commit | f8d5b377c8b1452c71d2766becad881f5541cda1 (patch) | |
| tree | 094b155809e241a78284847387fa06c57dd59b15 /src/amd/vulkan/radv_device.c | |
| parent | b86f86f55cef4672f23cb50871c8cec03deecbd6 (diff) | |
radv: set cb base tile swizzles for MRT speedups (v4)
This patch uses addrlib to workout the tile swizzles according
to the surface index. It seems to produce the same values as
amdgpu-pro for the deferred test.
v2: don't apply swizzle to CMASK. the eg docs don't mention
it, and we clearly don't align cmask for that.
v3: disable surf index for dedicated images, as these will
most likely be shared, and I don't think the metadata has
space for this info in it yet.
v4: update for shareable images, rename combined_swizzle
to tile_swizzle
This gets the deferred demo from 730->950fps on my rx480.
(dcc cmask elim predication patches get it further)
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_device.c')
| -rw-r--r-- | src/amd/vulkan/radv_device.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 2670d47fdb8..3b405838f39 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -2814,7 +2814,8 @@ radv_initialise_color_surface(struct radv_device *device, } cb->cb_color_base = va >> 8; - + if (device->physical_device->rad_info.chip_class < GFX9) + cb->cb_color_base |= iview->image->surface.u.legacy.tile_swizzle; /* CMASK variables */ va = device->ws->buffer_get_va(iview->bo) + iview->image->offset; va += iview->image->cmask.offset; @@ -2823,6 +2824,8 @@ radv_initialise_color_surface(struct radv_device *device, va = device->ws->buffer_get_va(iview->bo) + iview->image->offset; va += iview->image->dcc_offset; cb->cb_dcc_base = va >> 8; + if (device->physical_device->rad_info.chip_class < GFX9) + cb->cb_dcc_base |= iview->image->surface.u.legacy.tile_swizzle; uint32_t max_slice = radv_surface_layer_count(iview); cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) | @@ -2838,6 +2841,8 @@ radv_initialise_color_surface(struct radv_device *device, if (iview->image->fmask.size) { va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset; cb->cb_color_fmask = va >> 8; + if (device->physical_device->rad_info.chip_class < GFX9) + cb->cb_color_fmask |= iview->image->surface.u.legacy.tile_swizzle; } else { cb->cb_color_fmask = cb->cb_color_base; } |