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authorDave Airlie <[email protected]>2017-03-30 08:10:46 +0100
committerDave Airlie <[email protected]>2017-04-01 07:15:51 +1000
commitaeb49bc2b9e1d6f98b760a8cc3f208418b7f4349 (patch)
tree84a3ea4f699cd6897f1753d73225378fe975b44a /src/amd/vulkan/radv_cmd_buffer.c
parent46a820b383350bfaabde990e81f2086b040e0d13 (diff)
radv: port polaris vgt vertex reuse workaround.
This ports the VGT_VERTEX_REUSE register settings for Polaris GPUs from radeonsi. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c16
1 files changed, 16 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7d568e8c352..1116f24b1da 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -716,6 +716,21 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer,
}
}
+static void polaris_set_vgt_vertex_reuse(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_pipeline *pipeline)
+{
+ uint32_t vtx_reuse_depth = 30;
+ if (cmd_buffer->device->physical_device->rad_info.family < CHIP_POLARIS10)
+ return;
+
+ if (pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
+ if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD)
+ vtx_reuse_depth = 14;
+ }
+ radeon_set_context_reg(cmd_buffer->cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
+ vtx_reuse_depth);
+}
+
static void
radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline)
@@ -730,6 +745,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer,
radv_emit_vertex_shader(cmd_buffer, pipeline);
radv_emit_geometry_shader(cmd_buffer, pipeline);
radv_emit_fragment_shader(cmd_buffer, pipeline);
+ polaris_set_vgt_vertex_reuse(cmd_buffer, pipeline);
radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
pipeline->graphics.prim_restart_enable);