diff options
| author | Dave Airlie <[email protected]> | 2017-11-06 02:03:43 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-11-13 07:17:09 +0000 |
| commit | bec716e8441e3fcef71ce8f9d17d98ddf5a652e0 (patch) | |
| tree | 9885a1b6d4e3476ed47e334bc62f00b921b6f68d /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | 031e591923fad7792a4e2e0522cf63a3ff62bc69 (diff) | |
radv: emit esgs ring size in one place.
This register is the same on all gpus so far, so emit it in one
place and also for the pre-gfx9 gpus set the value in the pipeline
creation.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b1dbb04eaad..98f07e850e9 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -731,13 +731,11 @@ radv_emit_hw_vs(struct radv_cmd_buffer *cmd_buffer, static void radv_emit_hw_es(struct radv_cmd_buffer *cmd_buffer, - struct radv_shader_variant *shader, - struct ac_es_output_info *outinfo) + struct radv_pipeline *pipeline, + struct radv_shader_variant *shader) { uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset; - radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, - outinfo->esgs_itemsize / 4); radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); radeon_emit(cmd_buffer->cs, va >> 8); radeon_emit(cmd_buffer->cs, va >> 40); @@ -806,7 +804,7 @@ radv_emit_vertex_shader(struct radv_cmd_buffer *cmd_buffer, if (vs->info.vs.as_ls) radv_emit_hw_ls(cmd_buffer, vs); else if (vs->info.vs.as_es) - radv_emit_hw_es(cmd_buffer, vs, &vs->info.vs.es_info); + radv_emit_hw_es(cmd_buffer, pipeline, vs); else radv_emit_hw_vs(cmd_buffer, pipeline, vs); } @@ -826,7 +824,7 @@ radv_emit_tess_shaders(struct radv_cmd_buffer *cmd_buffer, if (tes) { if (tes->info.tes.as_es) - radv_emit_hw_es(cmd_buffer, tes, &tes->info.tes.es_info); + radv_emit_hw_es(cmd_buffer, pipeline, tes); else radv_emit_hw_vs(cmd_buffer, pipeline, tes); } @@ -915,6 +913,9 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer, S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0)); + radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, + pipeline->graphics.gs.vgt_esgs_ring_itemsize); + va = radv_buffer_get_va(gs->bo) + gs->bo_offset; if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { @@ -929,7 +930,6 @@ radv_emit_geometry_shader(struct radv_cmd_buffer *cmd_buffer, radeon_set_context_reg(cmd_buffer->cs, R_028A44_VGT_GS_ONCHIP_CNTL, pipeline->graphics.gs.vgt_gs_onchip_cntl); radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, pipeline->graphics.gs.vgt_gs_max_prims_per_subgroup); - radeon_set_context_reg(cmd_buffer->cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, pipeline->graphics.gs.vgt_esgs_ring_itemsize); } else { radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4); radeon_emit(cmd_buffer->cs, va >> 8); |