diff options
| author | Dave Airlie <[email protected]> | 2017-04-18 05:23:47 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-04-19 09:00:42 +1000 |
| commit | ec15e0d3015ccef4d6c60bd282cfb848118557ae (patch) | |
| tree | 7278acf1a57c9ce4b14591be30eb617365decb56 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | 31174069d2f0bbf016f3a581f4703b8c3417d0f0 (diff) | |
radv: optimise compute shader grid size emission.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 52b74539068..7056d0d0266 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2781,11 +2781,14 @@ void radv_CmdDispatch( MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { assert(!loc->indirect); - assert(loc->num_sgprs == 3); - radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3); + uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + assert(loc->num_sgprs == grid_used); + radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used); radeon_emit(cmd_buffer->cs, x); - radeon_emit(cmd_buffer->cs, y); - radeon_emit(cmd_buffer->cs, z); + if (grid_used > 1) + radeon_emit(cmd_buffer->cs, y); + if (grid_used > 2) + radeon_emit(cmd_buffer->cs, z); } radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) | @@ -2817,7 +2820,8 @@ void radv_CmdDispatchIndirect( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { - for (unsigned i = 0; i < 3; ++i) { + uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + for (unsigned i = 0; i < grid_used; ++i) { radeon_emit(cmd_buffer->cs, PKT3(PKT3_COPY_DATA, 4, 0)); radeon_emit(cmd_buffer->cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG)); @@ -2888,10 +2892,13 @@ void radv_unaligned_dispatch( struct ac_userdata_info *loc = radv_lookup_user_sgpr(cmd_buffer->state.compute_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_GRID_SIZE); if (loc->sgpr_idx != -1) { - radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3); + uint8_t grid_used = cmd_buffer->state.pipeline->shaders[MESA_SHADER_COMPUTE]->info.info.cs.grid_components_used; + radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, grid_used); radeon_emit(cmd_buffer->cs, blocks[0]); - radeon_emit(cmd_buffer->cs, blocks[1]); - radeon_emit(cmd_buffer->cs, blocks[2]); + if (grid_used > 1) + radeon_emit(cmd_buffer->cs, blocks[1]); + if (grid_used > 2) + radeon_emit(cmd_buffer->cs, blocks[2]); } radeon_emit(cmd_buffer->cs, PKT3(PKT3_DISPATCH_DIRECT, 3, 0) | PKT3_SHADER_TYPE_S(1)); |