diff options
| author | Dave Airlie <[email protected]> | 2017-06-06 09:01:48 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-06-06 09:43:40 +1000 |
| commit | c2fbeb7ca057b3bee8c8cd0f7076af2b90d28111 (patch) | |
| tree | 4e8263e1a9be4ba109e76008bdafe642778db081 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | b11c4a554681607bbec67f45442b815b51573236 (diff) | |
radv: add GFX9 cache flushing support.
GFX9 needs to write event EOP to a fence buffer, allocate some
space for this, and just write an ever increasing number to it,
this isn't exactly what radeonsi does, but it seems to work.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index d66f8979e8f..d078421182d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -234,6 +234,14 @@ static void radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer) cmd_buffer->record_fail = false; cmd_buffer->ring_offsets_idx = -1; + + if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { + void *fence_ptr; + radv_cmd_buffer_upload_alloc(cmd_buffer, 8, 0, + &cmd_buffer->gfx9_fence_offset, + &fence_ptr); + cmd_buffer->gfx9_fence_bo = cmd_buffer->upload.upload_bo; + } } static bool |