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authorDave Airlie <[email protected]>2016-10-25 07:23:48 +0100
committerDave Airlie <[email protected]>2016-11-23 10:16:34 +1000
commitea417f53354b5ea65c7c4863a4f336dda23bf019 (patch)
tree7d7d0e2cfed1bf73b22923a63fee0f3b740e2bda /src/amd/vulkan/radv_cmd_buffer.c
parent3fd79558beb3ab156882a206d5a6027fa9db4af7 (diff)
radv: move pipeline barrier image transitions after src flushing
This seems like it would conform better with the spec. noticed while digging into fast clears. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 9517e7a13da..824f9d80af8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2246,19 +2246,11 @@ void radv_CmdPipelineBarrier(
}
for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
- RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
src_flags |= pImageMemoryBarriers[i].srcAccessMask;
dst_flags |= pImageMemoryBarriers[i].dstAccessMask;
-
- radv_handle_image_transition(cmd_buffer, image,
- pImageMemoryBarriers[i].oldLayout,
- pImageMemoryBarriers[i].newLayout,
- pImageMemoryBarriers[i].subresourceRange,
- 0);
}
enum radv_cmd_flush_bits flush_bits = 0;
-
for_each_bit(b, src_flags) {
switch ((VkAccessFlagBits)(1 << b)) {
case VK_ACCESS_SHADER_WRITE_BIT:
@@ -2277,6 +2269,18 @@ void radv_CmdPipelineBarrier(
break;
}
}
+ cmd_buffer->state.flush_bits |= flush_bits;
+
+ for (uint32_t i = 0; i < imageMemoryBarrierCount; i++) {
+ RADV_FROM_HANDLE(radv_image, image, pImageMemoryBarriers[i].image);
+ radv_handle_image_transition(cmd_buffer, image,
+ pImageMemoryBarriers[i].oldLayout,
+ pImageMemoryBarriers[i].newLayout,
+ pImageMemoryBarriers[i].subresourceRange,
+ 0);
+ }
+
+ flush_bits = 0;
for_each_bit(b, dst_flags) {
switch ((VkAccessFlagBits)(1 << b)) {