diff options
| author | Dave Airlie <[email protected]> | 2017-03-28 11:34:19 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-03-28 17:40:14 +1000 |
| commit | 8996fdbf61e5341c321c802278ee388ac5001f50 (patch) | |
| tree | a7eacc1fb244766b9ede938c6d04e95db9b6a6f2 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | cd33a5c1cb68d8c7e67f4724cc19bb92a405c796 (diff) | |
radv: move db_shader_control calculation to pipeline.
There is no need to recalculate this every time.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 195a82fef57..8e35dc5299b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -674,7 +674,6 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); struct radv_blend_state *blend = &pipeline->graphics.blend; unsigned ps_offset = 0; - unsigned z_order; struct ac_vs_output_info *outinfo; assert (pipeline->shaders[MESA_SHADER_FRAGMENT]); @@ -692,21 +691,8 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer, radeon_emit(cmd_buffer->cs, ps->rsrc1); radeon_emit(cmd_buffer->cs, ps->rsrc2); - if (ps->info.fs.early_fragment_test || !ps->info.fs.writes_memory) - z_order = V_02880C_EARLY_Z_THEN_LATE_Z; - else - z_order = V_02880C_LATE_Z; - - radeon_set_context_reg(cmd_buffer->cs, R_02880C_DB_SHADER_CONTROL, - S_02880C_Z_EXPORT_ENABLE(ps->info.fs.writes_z) | - S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.fs.writes_stencil) | - S_02880C_KILL_ENABLE(!!ps->info.fs.can_discard) | - S_02880C_MASK_EXPORT_ENABLE(ps->info.fs.writes_sample_mask) | - S_02880C_Z_ORDER(z_order) | - S_02880C_DEPTH_BEFORE_SHADER(ps->info.fs.early_fragment_test) | - S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) | - S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory)); + pipeline->graphics.db_shader_control); radeon_set_context_reg(cmd_buffer->cs, R_0286CC_SPI_PS_INPUT_ENA, ps->config.spi_ps_input_ena); |