diff options
author | Bas Nieuwenhuizen <[email protected]> | 2017-06-03 00:01:36 +0200 |
---|---|---|
committer | Bas Nieuwenhuizen <[email protected]> | 2017-06-03 22:24:37 +0200 |
commit | 4415a46be2cbb752b94b62bdf5bc7d4d4bbe9fab (patch) | |
tree | c1ceeb23ebad8c05702865c3bb1bbce1dda219b4 /src/amd/vulkan/radv_cmd_buffer.c | |
parent | 5fb8bb306534d633ceb4e33d89984718326773ba (diff) |
radv: Dirty all descriptors sets when changing the pipeline.
Sets could have been ignored during previous descriptor set flush
due to the shader not using them and therefore no SGPR being assigned.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Fixes: ae61ddabe8c "radv: move userdata sgpr ownership to compiler side."
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
-rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 17 |
1 files changed, 12 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 0f7b754da97..6826ec5aa37 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -2186,6 +2186,13 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer) assert(cmd_buffer->cs->cdw <= cdw_max); } +static void radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer) +{ + for (unsigned i = 0; i < MAX_SETS; i++) { + if (cmd_buffer->state.descriptors[i]) + cmd_buffer->state.descriptors_dirty |= (1u << i); + } +} void radv_CmdBindPipeline( VkCommandBuffer commandBuffer, @@ -2195,10 +2202,7 @@ void radv_CmdBindPipeline( RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline); - for (unsigned i = 0; i < MAX_SETS; i++) { - if (cmd_buffer->state.descriptors[i]) - cmd_buffer->state.descriptors_dirty |= (1u << i); - } + radv_mark_descriptor_sets_dirty(cmd_buffer); switch (pipelineBindPoint) { case VK_PIPELINE_BIND_POINT_COMPUTE: @@ -2207,6 +2211,9 @@ void radv_CmdBindPipeline( break; case VK_PIPELINE_BIND_POINT_GRAPHICS: cmd_buffer->state.pipeline = pipeline; + if (!pipeline) + break; + cmd_buffer->state.vertex_descriptors_dirty = true; cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE; cmd_buffer->push_constant_stages |= pipeline->active_stages; @@ -2369,7 +2376,6 @@ void radv_CmdSetStencilReference( cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE; } - void radv_CmdExecuteCommands( VkCommandBuffer commandBuffer, uint32_t commandBufferCount, @@ -2414,6 +2420,7 @@ void radv_CmdExecuteCommands( primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL; primary->state.last_primitive_reset_en = -1; primary->state.last_primitive_reset_index = 0; + radv_mark_descriptor_sets_dirty(primary); } } |