diff options
| author | Bas Nieuwenhuizen <[email protected]> | 2017-03-08 21:31:53 +0100 |
|---|---|---|
| committer | Bas Nieuwenhuizen <[email protected]> | 2017-03-09 02:35:01 +0100 |
| commit | dd094e4ff9ff0967b515a4330e40feca55247e25 (patch) | |
| tree | 9a39364e01f1a32bf6abb6e4fceddf9147ee5a43 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | b075eb7d476eb750092f72e7ec65bc41003fa658 (diff) | |
radv: Invalidate the correct caches for CB/DB dst barriers.
Signed-off-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 07d0a0c2c12..088a3c9025c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1497,13 +1497,19 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1; break; case VK_ACCESS_SHADER_READ_BIT: - flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2; - break; - case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT: case VK_ACCESS_TRANSFER_READ_BIT: - case VK_ACCESS_TRANSFER_WRITE_BIT: case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT: - flush_bits |= RADV_CMD_FLUSH_AND_INV_FRAMEBUFFER | RADV_CMD_FLAG_INV_GLOBAL_L2; + flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | + RADV_CMD_FLAG_INV_GLOBAL_L2; + break; + case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT: + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB | + RADV_CMD_FLAG_FLUSH_AND_INV_CB_META; + break; + case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT: + flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_DB | + RADV_CMD_FLAG_FLUSH_AND_INV_DB_META; + break; default: break; } |