diff options
| author | Dave Airlie <[email protected]> | 2017-03-28 05:53:50 +1000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-03-28 17:39:55 +1000 |
| commit | ae0551b4b3f7ca79148f0cb8384c0f1efc3faac2 (patch) | |
| tree | 9b3ba864507dd328bd7a61b3080ce6c5596a09d0 /src/amd/vulkan/radv_cmd_buffer.c | |
| parent | a8b8e542c2e9ea97413095993cee5ec8faf2ee16 (diff) | |
radv: fix ia_multi_vgt_param for instanced vs indirect draw.
The logic was different than radeonsi, fix it up before adding
tess support.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
| -rw-r--r-- | src/amd/vulkan/radv_cmd_buffer.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 1b13ae7bc64..eb2a7b0ddea 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1317,7 +1317,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, } static void -radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool instanced_or_indirect_draw, +radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, + bool instanced_draw, bool indirect_draw, uint32_t draw_vertex_count) { struct radv_pipeline *pipeline = cmd_buffer->state.pipeline; @@ -1382,7 +1383,7 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer, bool instanced_o if (cmd_buffer->state.dirty & (RADV_CMD_DIRTY_DYNAMIC_SCISSOR)) radv_emit_scissor(cmd_buffer); - ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_or_indirect_draw, draw_vertex_count); + ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count); if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) { if (cmd_buffer->device->physical_device->rad_info.chip_class >= CIK) radeon_set_context_reg_idx(cmd_buffer->cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param); @@ -2296,7 +2297,7 @@ void radv_CmdDraw( { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), vertexCount); + radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, vertexCount); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10); @@ -2347,7 +2348,7 @@ void radv_CmdDrawIndexed( uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size; uint64_t index_va; - radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), indexCount); + radv_cmd_buffer_flush_state(cmd_buffer, (instanceCount > 1), false, indexCount); radv_emit_primitive_reset_index(cmd_buffer); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15); @@ -2445,7 +2446,7 @@ radv_cmd_draw_indirect_count(VkCommandBuffer command uint32_t stride) { RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); - radv_cmd_buffer_flush_state(cmd_buffer, true, 0); + radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 14); @@ -2470,7 +2471,7 @@ radv_cmd_draw_indexed_indirect_count( int index_size = cmd_buffer->state.index_type ? 4 : 2; uint32_t index_max_size = (cmd_buffer->state.index_buffer->size - cmd_buffer->state.index_offset) / index_size; uint64_t index_va; - radv_cmd_buffer_flush_state(cmd_buffer, true, 0); + radv_cmd_buffer_flush_state(cmd_buffer, false, true, 0); radv_emit_primitive_reset_index(cmd_buffer); index_va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->state.index_buffer->bo); |